A reduced state equalizer operates on a trellis to estimate a sequence of transmitted symbols, typically using either the Viterbi or BCJR algorithm. The trellis has a number of states at each symbol time, the number of states being a function of the modulation. For example, assuming that the channel has a memory of one-symbol period, a trellis has 64 different states for 64-QAM (quadrature amplitude modulation) and 32 possible states for 32-QAM. Reduced state equalizers prune the trellis when determining the most likely path associated with a sequence of transmitted symbols. By pruning the trellis, the metrics of many paths in the trellis are not evaluated when determining the most likely path, reducing computational complexity. However, soft bit value generation becomes less reliable when trellis paths go unevaluated. This in turn makes it very difficult to obtain accurate probability estimates for the transmitted binary bits within each symbol.
The use of reduced-state equalizers continues to grow as modern wireless communication systems transmit increasingly more bits per symbol. Having a higher symbol bit density exponentially grows the number of paths in the trellis which makes MLSE (Maximum Likelihood Sequence Estimation) and even DFSE (Decision-Feedback Sequence Estimation) equalizers less practical. For example, consider 64-QAM. Each 64-QAM symbol carries 6 bits which is spectrally much more efficient than e.g. GMSK which carries only 1 bit per symbol. However, since each symbol can have one of 64 possible values, the corresponding trellis has 64×64 possible paths from one symbol time to the next symbol time considering the most current two taps of the channel. The DFSE equalizer reduces the number of states by shortening the channel impulse response. For example, the DFSE equalizer truncates the radio channel impulse response length from 7 taps to 2 taps. This way, the number of trellis states evaluated each iteration is reduced from M^7 to M^2 where M is the modulation size. Other reduced-state equalizers such as RSSE (Reduced-State Sequence Estimation) and MA (M-Algorithm) provide similar computational savings. DFSE, RSSE, MA and other types of conventional reduced-state equalizers generate soft bit values each iteration as the trellis is being extended from the current symbol time to the next symbol time. Yet, not all paths between the two symbol times are evaluated by such conventional reduced-state equalizers. Under some conditions, e.g. when the radio channel is effectively shortened to 2 symbols, DFSE can be considered a full-trellis equalizer, i.e. M×M paths are evaluated each iteration. In contrast, RSSE and MA do not have M×M paths but rather G×M paths. The missing paths of the RSSE and MA change constantly each iteration.
The accuracy of the soft bit values generated by a reduced-state equalizer is a function of the number of paths evaluated by the equalizer. A soft bit value is associated with a particular bit within a symbol and is defined as the ratio between the probability that the bit has a “0” value and the bit has a “1” value. If the bit is more likely to be a “0”, the ratio is larger than 1 and the log of the ratio is larger than 0, i.e. a positive soft bit value indicates that a bit is more likely to be a “0”. With sequence estimation, the equalizer determines the most likely symbol sequence. Each symbol has multiple bits and individual bits of the same symbol have in general different log-likelihood ratios, i.e. soft bit values. A good approximation of the optimum soft bit value, i.e. log-likelihood ratio, is obtained by using a so-called simplified SOVA (soft output viterbi) algorithm. Soft bit value accuracy decreases when less than all of the possible paths are evaluated. In some cases, the accuracy of the soft bit values can degrade so poorly that they become unreliable, e.g. when an entire set of paths goes unevaluated. Accordingly, there is a need for a reduced-state equalizer that produces reliable soft bit values.